In recent years, as the number of transistors mounted on a semiconductor device increases, it is desired to reduce power consumption of a semiconductor device. For example, it is known to prevent occurrence of a current flowing from a positive power source VDD to a negative power source VSS by controlling a pMOS transistor and an nMOS transistor connected in series between a pair of power source points including the positive power source VDD and the negative power source VSS so as to not turn on at the same time.
Further, the degree of miniaturization of a transistor mounted on a semiconductor device increases and the ratio accounted for by a leak current of a transistor in the amount of power consumption increases, and therefore, a reduction in the leak current of a transistor has become a big challenge in power saving of a semiconductor device.
In a semiconductor device referred to a system LSI, a large number of memory cells, such as SRAM cells, are mounted, and therefore, it is desired to reduce the leak current of the memory cells for power saving of the system LSI.
The power source of a memory cells which are not in use are turned off, in order to reduce the leak current of the memory cells. However it is desirable for the memory cells to store data even while not in use, and therefore, it is not preferable to turn off the power source of the memory cells even if the memory cells are not in use.
In such circumstances, it is known to supply power to memory cells from two power sources, i.e., a normal power source and a sleep power source in order to reduce the leak current of the memory cells. When the memory cells are not in use, the normal power source is switched to the sleep power source having an electric potential about 0.01 V higher than that of the normal power source that is grounded. Then, it is possible to reduce the leak current by reducing the voltage applied to the memory cell when the memory cells are not in use.